DFM Checklist for PCB Designers

Design for Repeatable Manufacturing

DFM designs the PCB so it can be fabricated, assembled, inspected, tested and repeated reliably.

1. Requirements
2. Stack-up
3. Libraries
4. Placement
5. Routing
6. Output Data
7. Supplier DFM
8. Qualified Release

DFM • DFA • DFT • DFR

DFM Fabrication	DFA Assembly	Dft Test	Dfr Reliability
Trace/space control • Drilling quality and alignment • Annular ring integrity • Stack-up and layer registration • Solder mask definition • Surface finish compatibility • HDI and microvia feasibility	Land pattern fit and paste • Component spacing and keepouts • Polarity and orientation • Thermal balance and heat paths • Solder paste volume control • Pick-and-place access and fiducials	Accessible test points • Net access for test and probe • Boundary scan readiness • Fixture strategy and clearance • In-circuit and functional test • Programming / firmware access	Material selection and compatibility • Via reliability and structure • Thermal cycling and stress • CAF risk management • Current carrying and copper balance • Safety spacing and creepage

Gate 1 — Before Layout

Item	Detail
Function, environment & life	Define what the product does, where it will live and how long it must last.
Board technology	Select layer count, HDI needs, materials, finishes and stack-up approach.
Product class & customer specs	Understand class level, standards and any governing requirements.
Target fabricator / assembler	Engage early and align on capabilities and process expectations.
Volumes	Prototype, low, medium or high volume — plan the process accordingly.
Outline, thickness & mechanicals	Board outline, cutouts, mounting, connectors and thickness targets.
Temperature, humidity & vibration	Operating range, storage, shock and vibration requirements.
Voltage, current & power	Supply rails, power delivery, limits and protection strategy.
High-speed, RF & impedance	Pair geometry, reference planes and controlled impedance needs.
Reliability & reflow considerations	Reflow profile, reliability risks and thermal constraints.
Test & programming strategy	How the board will be tested, inspected and programmed.

Preferred vs Absolute Minimum

Preferred Production Rule

• Routine default for production.
• Provides stronger yield margin and process robustness.

Design to preferred rules for repeatable results.

Absolute Minimum

• Use only when absolutely necessary.
• Must be justified and reviewed against exact:
• Layer count
• Board thickness
• Material system
• Copper weights

Exceptions require engineering review and manufacturer buy-off.

The goal is not a board that can be built once – It is a design that can be built repeatedly without hidden CAM edits or supplier heroics.

Start DFM with architecture — not after the Gerbers are generated.

DFM Checklist for PCB Designers

Stack-up • Libraries • Placement • Mechanics

1 Stack-up & Materials

Item	Detail
Realistic fabricator build	Use build capability you can buy. Avoid unusual combinations.
Adequate layer count	Use the fewest layers that meet electrical and manufacturing needs.
Finished thickness & tolerance	Specify target finished thickness and tolerance based on assembly and performance needs.
Core / prepreg family	Specify material family consistently across the stack per performance class.
Copper weights vs etch capability	Match copper weights to etch capability and aspect-ratio limitations.
Continuous references	Ensure solid ground/power references on adjacent layers where required.
Practical impedance geometry	Maintain manufacturable trace width, spacing and dielectric to meet targets.
Dk / Df / roughness / weave	Account for dielectric constant, loss tangent, surface roughness and weave.
Tg / Td / z-CTE / moisture	Select materials that meet temperature, reliability and moisture requirements.
Hybrids & substitutions controlled	Specify alternatives and approvals for equivalent materials.

2 Library & Footprint Integrity

Item	Detail
Use current datasheet	Verify package and recommended land pattern from latest datasheet.
Symbol-to-pin match	Ensure schematic symbol matches footprint pins and functions.
Polarity & pin 1 defined	Show pin 1, polarity marks and orientation clearly.
Pad / paste / mask geometry	Pads, paste apertures and solder mask expansion are correct.
Body / courtyard defined	Provide accurate body, courtyard and component keep-out.
Thermal-pad & paste windows	Thermal pads use appropriate paste window patterns.
Via-in-pad fill / cap options	Define via-in-pad as filled, capped or tented per assembly process.
PTH finished hole specified	Provide finished hole size and plated status for through-hole pins.
Press-fit connectors defined	Specify hole finish, plating type and press-fit requirements.
Npth / PTH / slots correct	Differentiate NPTH, PTH and slots; sizes and tolerances defined.
Height & keep-outs checked	Account for component height, standoffs and mechanical keep-outs.

3 Placement / DFA

Item	Detail
Clearances to enclosure / connectors / fasteners / edges	Maintain adequate clearance for mating parts and mechanical features.
BGA escape & component density	Ensure routing escape, dog-bone room and assembly access.
Thermal mass & heavy components	Place heavy or tall parts near supports; consider board flex.
Heat path & airflow	Provide heat paths to copper, vias and airflow where required.
Analogue / RF separation	Separate sensitive circuits; control return paths and coupling.
Decoupling close & short returns	Place decoupling close to power pins with short, wide returns.
Test / programming / rework access	Provide access for test points, programming headers and component rework.
Wave / selective solder orientation	Orient components for reliable soldering and avoid shadowing.
Panelisation / rails / tooling	Support tooling, depaneling and handling without damaging the board.

4 Outline & Mechanical Features

Item	Detail
One closed contour	Use a single, closed board outline without overlaps or gaps.
Cut-outs & slots defined	Define cut-outs, slots and keep-outs precisely.
Router radius applied	Apply inside/outside router radius to all corners and cut-outs.
V-score only on straight suitable boundaries	Place V-score on straight lines with adequate copper-to-score relief.
Castellations / edge plating / plated slots	Identify requirements and finishes clearly.
Bevel / chamfer AS required	Specify bevels or chamfers for fit and safety.
Copper-to-edge clearance	Maintain adequate copper-to-edge clearance per fabricator capability.
Mechanical datums & tolerances	Define datums, critical dimensions and tolerances for assembly features.
Mouse bites away from sensitive features	Place mouse bites away from pads, traces and keep-outs.

Board Outline – Correct vs Ambiguous

Correct	Ambiguous
One closed contour. Clear and unambiguous.	Open contours, overlaps or gaps cause confusion and rework.

Slots – Plated vs Non-Plated

Plated Slot	Non-Plated Slot
Annular ring present. Plated through.	No annular ring. Non-plated through.

A perfect route cannot rescue a bad footprint, ambiguous outline or unrealistic stack-up.

Good DFM decisions here mean fewer questions later — And fewer spins.

DFM Checklist for PCB Designers

Copper Geometry • Safety Spacing • Signal Integrity

Trace Width & Spacing

Item	Detail
Selected copper weight & finished copper	Use the copper weight and target finished thickness specified for fabrication.
Preferred supplier capability	Design to your fabricator’s proven capability, not theoretical limits.
Intentional short neck-downs	Keep neck-downs short and symmetric; avoid unintended aspect-ratio jumps.
No manual etch compensation unless agreed	Leave sizing to the manufacturer unless explicitly provided and documented.
Avoid risky acute wedges / slivers	Remove copper slivers and extremely acute angles that create etch, reliability and probe risks.
Robust trace-to-pad junctions	Use teardrops or wide connections to reduce stress, improve reliability and plating quality.
High-current sizing	Size copper for current, temperature rise and DC/AC loss per the actual board conditions.
Copper balance	Distribute copper area and density to minimise warpage and process variation.
Plane necks reviewed	All plane neck-downs are intentional, analysed and approved for current and thermal performance.

Thin-copper capability does not automatically apply to heavy copper.

Clearance ≠ Creepage

Item	Detail
Manufacturing etch spacing (clearance)	Minimum spacing to reliably manufacture the board without unintended shorts.
Functional electrical clearance	Minimum air/gas spacing to prevent arcing, breakdown or tracking between potentials.
Surface creepage distance	Minimum path along the surface to resist leakage currents in the presence of contamination.

• Board edge
• Mounting hardware
• Slots & cutouts
• Contamination environment

Consider board-edge exposure, mounting hardware, slots/cutouts and contamination environment.

Solder mask is not a universal substitute for safety spacing.

Controlled Impedance

Item	Detail
Controlled nets & tolerance defined	Impedance targets, tolerance and test method are specified.
Single-ended / differential unambiguous	Clearly define net types; avoid mixed or ambiguous routing.
Reference continuous	Maintain an unbroken reference plane under controlled impedance routes.
Width / gap based on production stack-up	Use the fabricator’s stack-up data, not generic assumptions.
Fabricator adjustments controlled	Manufacturer may adjust within capability; changes are communicated and recorded.
Impedance coupons included	Provide test coupons at defined locations.
Return vias at transitions	Place return vias near layer transitions to maintain reference integrity.
Pad / antipad margin adequate	Ensure annular ring and antipad sizes support impedance and reliablility.
Solder mask, Dk & roughness documented	Material and process parameters that affect impedance are defined.

Differential Pairs

Item	Detail
Same layer except intentional transition	Route pairs together on the same layer whenever practical.
Symmetric signal vias / anti-pads / reference vias	Keep via structures and clearances symmetric and matched.
Spacing to aggressors	Maintain adequate isolation from other signals and switching nets.
Sensible length tuning	Length-match within tolerance using reasonable tuning; avoid dense serpentine packing.
Neck-down impact checked	Short neck-downs in pairs shall be matched in length and offset.
BGA / connector launches reviewed	Ensure symmetric fan-out, breakout and via placement.
Weave skew reviewed	Weave patterns are symmetric; skew minimised and controlled.

Planes & Power

Item	Detail
No isolated copper islands	Remove floating islands that can cause etch, reliability and EMI issues.
Thermal relief suits solderability & current	Use thermal reliefs appropriate for assembly and current load.
Adequate spoke width & count	Thermal relief spokes are wide and numerous enough to carry required current.
No unintended current bottlenecks	Avoid narrow necks and pinch points in power and ground paths.
Split planes do not break high-speed returns	Provide stitching and return paths to maintain signal integrity.
Copper balance maintained	Balance plane areas across the board to minimise warpage.

Fabrication capability is not electrical-safety compliance.

Route to the real stack-up – Not a placeholder geometry.

Design for manufacturability, reliability and safety — then verify with your fabricator early.

DFM Checklist for PCB Designers

Vias • Mask • Finish • Special Technologies

Via / Drill Gate

Item	Detail
Finished hole vs production drill	Design based on the finished hole, not the drill size.
Preferred mechanical drill	Use mechanical drills where possible; avoid reliance on non-standard tools.
Acceptable aspect ratio	Ensure via and hole aspect ratios are acceptable for the build.
Annular-ring margin	Provide sufficient annular ring for reliability and plating build.
Internal / external registration	Account for layer-to-layer and panel registration tolerances.
Drill-to-copper / drill-to-drill	Maintain required clearances between drills and to copper features.
Npth clearance	Specify adequate clearance for NPTH from copper.
Via architecture matches lamination	All via types and depths are compatible with the stack-up.
Blind / buried start-stop layers	Start and stop layers are defined and manufacturable.
Laser microvia depth & lands	Depth to target layer and capture lands are adequate.
Stacked microvias qualified	Stacked microvia configurations are qualified.
Via-in-pad fill / cap	Filled and capped vias in pads are defined and acceptable.
Backdrill side / depth / residual stub	Backdrill side, depth and residual stub are controlled.
Press-fit finished hole / plating	Press-fit holes are sized for the finished hole and plating build.
Plated slots correct	Plated slots are defined with end radii and plating requirements.

Solder Mask & Legend

Item	Detail
Supplier-compatible expansion	Mask expansion accounts for registration and process.
Manufacturable mask dams	Solder mask dams are wide enough to be consistent.
Intentional merged openings	Merges are intentional and reviewed.
Explicit tent / plug / fill	Tent, plug and fill requirements are explicitly specified.
Vippo not merely tented	Via-in-pad-plated over is defined for fill / cap.
Edge fingers exposed	Edge fingers are free of mask and fully exposed.
Mask-defined / copper-defined	Pad definition is intentional and appropriate.
Legend off solderable pads	Silkscreen is clear of solderable surfaces.
Readable markings	Polarity, part ID, revision and orientation are clear and legible.

Surface Finish & Edge Features

Item	Detail
Finish chosen for application	Finish suits pitch, storage, assembly, bonding/contact and environment.
Hard gold / selective plating controlled	Thickness and coverage are defined and controlled.
RF compatibility	Finish and surface planarity support RF performance.
Edge bevel defined	Bevels are specified for handling and assembly.
Castellations defined	Castellations are dimensioned and oriented.
Edge plating defined	Edge plating requirements are specified.
Edge copper clearance	Copper keepout from the edge is adequate.

Thermal / Heavy Copper

Item	Detail
Heat path defined	Heat flow and dissipation paths are intentional.
Thermal-via strategy	Via diameter, pitch, count and fill are specified.
Paste windows defined	Paste windows are placed for thermal conductance.
Thermal masses considered	Large copper areas are reviewed for balance and serviceability.
Temperature rise acceptable	Expected rise is within allowable limits.
Trace / space reflect copper thickness	Widths and spacing reflect copper thickness.
Current-carrying features adequate	Via arrays, terminals and plane connections can carry required current.
Copper balanced	Copper distribution is balanced to control warp.

HDI / BGA / RF / Flex

Item	Detail
Use HDI only when justified	HDI is used where it provides clear benefit.
Minimise sequential laminations	Sequential builds are minimised and justified.
BGA escape robust	Escape routing is not dependent on fragile minimums.
RF design controlled	Material, foil, geometry and CAM changes are controlled.
Flex design reviewed	Bends, copper relief, coverlay and stiffeners are reviewed.
Transitions defined	Rigid-flex and material transitions are controlled.

Special processes must be inside the intended fabricator’s qualified window – Not merely technically possible.

• Design for build
• Verify early
• Document clearly
• Stay within capability
• Avoid assumptions
• Drive reliability

DFM Checklist for PCB Designers

Drawing • Output Data • Assembly • Test Readiness

Fabrication Drawing

Item	Detail
Dimensions / tolerances	Not over-constrained; practical and manufacturable.
Datum / origin	Clear datum(s) and coordinate origin defined.
Finished thickness	Overall finished board thickness specified.
Material / substitution	Material system and allowable substitutions identified.
Layers / copper	Layer count and outer copper weights defined.
Finish	Surface finish and requirements specified.
Product class / standard / revision	Product class, governing standard and revision stated.
Finished-hole basis	Finished-hole requirement (e.g., PTH) defined.
Impedance table	Controlled impedances and tolerances provided.
Special vias / fill / backdrill	Requirements for via types, fill and backdrill stated.
Edge features	Slots, cut-outs, chamfers, radii and tooling defined.
Markings	Legend, polarity, orientation and IDs specified.
Coupons / test features	Coupons, test points and verification features defined.
No conflict with electronic data	All drawing notes agree with netlist and stack-up data.

Release Package

Item	Detail
Gerber X2 or ODB++ / IPC-2581	Generated from released database.
Plated / non-plated drills and routes	All holes, routes and slots included.
Drill map agrees	Drill map matches drill files and drawing.
Fabrication drawing agrees	Files agree with fabrication drawing.
Stack-up / impedance agree	Stack-up and impedance data included and consistent.
IPC-356 or equivalent netlist	Where appropriate for the product.
Readme / manifest	File list, units, revision, notes and approvals included.
One outline	Single outline file defines the board perimeter.
Consistent origin / units	All files share the same origin and units.
No obsolete files	Only current, released files are included.
Controlled archive	Released package stored in controlled archive.

Visual Output Review

Item	Detail
Every copper layer	Inspect each copper layer for correctness.
Mask versus pads / vias	Solder mask openings align with pads and vias.
Legend / paste	Silkscreen and paste layers are correct.
Drill overlay	Drill hits all features; no misregistration.
PTH / npth	Plated and non-plated holes as specified.
Slots / routes / cut-outs	Shapes complete and within board outline.
Outline	Board outline matches the fabrication drawing.
Plane polarity / voids	Plane polarities correct; voids as intended.
Special drill / backdrill	Backdrill depths and exclusions verified.
Missing flashes / zero-width lines	Check for missing pours, slivers and opens.
Compare to source database	Verify outputs against the released database.

Assembly / DFA

Item	Detail
Pad / paste / mask	Proper land pattern and apertures for process.
Thermal-pad paste	Paste reduction or windowing considered.
Tombstoning / thermal balance	Component balance and copper distribution OK.
Wave / selective keep-outs	Protective masks and keep-outs defined.
Through-hole solder access	Component and hole annular rings accessible.
Bottom retention	SMD retention on bottom side considered.
Spacing / rework	Minimum spacing and rework clearance met.
Fiducials	Fiducials provided and placed appropriately.
Panel tooling	Tooling holes, rails and references defined.
Moisture-sensitive / high-mass	Moisture and mass considerations addressed.

Dft & Bare-Board Test

Item	Detail
Critical net access	Key nets accessible for test.
Probe-compatible test points	Adequate, labelled test points provided.
Power / ground access	Power and ground nets testable.
Programming / debug	Access for programming and debug maintained.
Boundary scan	Scan chains and test headers supported.
Fixture keep-outs	Keep-outs for clamps, pins and bed-of-nails.
Traceable names	Net and component references are traceable.
Independent netlist	Test netlist matches the released database.
Intentional net ties	Specify and document shorted nets.
100% electrical test	Bare-board test plan for 100% electrical test.
Isolation / test-report requirements	Isolation criteria and test-report deliverables.

Panelisation

Item	Detail
Allow fabricator optimisation	Unless contractually fixed, allow practical optimisation.
Rails / tooling / fiducials	Rails, tooling holes and fiducials defined.
V-score / tab strategy	Break-apart method and tab locations defined.
Breakaway forces	Target breakaway force and method specified.
Coupons	Panel coupons and test features included.
Copper balance / thieving	Balance strategy and thieving as required.
Array drawing agrees	Panel array drawing matches assembly intent.
Single-board data agrees	Panel outputs match the single-board data.
Identify sides / polarity	Identify panel sides and polarity/orientation.

A perfect layout can still fail when release files are incomplete, contradictory or stale.

• Draw it right
• Output it right
• Build it right
• Test it right
• Document it right
• Deliver it right

DFM Checklist for PCB Designers

Severity • Red Flags • Qualification • Controlled Release

Critical	Major	Moderate	Minor	Advisory
Open/short, safety, noncompliance or major reliability risk; Stop release.	Outside preferred capability or significant yield/assembly risk; resolve with approval.	Manufacturable but weak margin/cost concern; improve or document.	Low-risk documentation/optimisation issue; correct before package.	Supplier preference/future improvement; record and feed back.

• Critical
• Major
• Moderate
• Minor
• Advisory

Red Flags — Stop Release

• Unreviewed non-standard stack-up or HDI.
• Absolute-minimum design on critical feature.
• Ambiguous finished-hole size or plating.
• Unchecked press-fit or mechanical tolerance.
• Impedance routed before real stack-up.
• Critical material substitution without SI review.
• Unqualified stacked microvias (buried/stacked).
• Revision mismatch across docs, files or BOM.
• Unexplained CAM change to functional copper.
• Unresolved DRC violations (critical or major).
• Safety spacing justified only by etch capability.
• Obsolete or superseded files in the data set.
• Unchecked or unverified critical footprint.

Trial / First Article

• Close supplier DFM and deviations first.
• Record actual stack-up and material.
• Inspect dimensions, holes and impedance.
• Microsections / annular ring evaluation.
• Solder mask, silkscreen and fine features.
• Board bow, twist and surface finish.
• Electrical test yield and diagnostic review.
• Assembly behaviour and mechanical fit.
• Feed lessons into rules, guidelines and AVL.

Sign-Off Owners

Owner	Status	Evidence
Requirements / Quality	(checkbox)	(document)
Stack-up / Fabricator	(checkbox)	(document)
Libraries / CAD Data	(checkbox)	(document)
Mechanical / Enclosure	(checkbox)	(document)
SI / PI Analysis	(checkbox)	(document)
Fabrication DFM	(checkbox)	(document)
Assembly DFA	(checkbox)	(document)
Test DFT	(checkbox)	(document)
Qualification	(checkbox)	(document)
Configuration Control	(checkbox)	(document)

• Requirements / Quality
• Stack-up / Fabricator
• Libraries / CAD Data
• Mechanical / Enclosure
• SI / PI Analysis
• Fabrication DFM
• Assembly DFA
• Test DFT
• Qualification
• Configuration Control

1. Define requirements & objectives
2. Select supplier technology
3. Create realistic stack-up
4. Set preferred ECAD rules
5. Verify libraries & CAD data
6. Place components (DFA)
7. Route with constraints (SI / PI)
8. Run Drc / DFM
9. Generate production data set
10. Visual cross-check & review
11. Supplier DFM review & feedback
12. Document controlled deviations
13. Trial build / FAI
14. Feed back to rules, AVL & BOM

Do not release until every critical and major issue is closed, every output matches the released database, and every supplier change is under configuration control.

Design to qualified capability • make exceptions deliberately • verify the package • learn from production.