Foundation • Building Blocks • Engineering Impact

A PCB stack-up is the planned vertical construction of copper layers, cores, prepregs, solder mask and specialised build-up structures.

• Solder mask
• Outer copper
• Prepreg
• Inner copper
• Core
• Inner copper
• Prepreg
• Outer copper
• Solder mask

Building Blocks of a PCB Stack-up

Item	Detail
Copper	Signals, references, power and shielding
Core	Fully cured copper-clad laminate
Prepreg	Resin system that bonds layers during lamination
Solder mask	Affects outer-layer impedance modelling
Build-up layers	HDI, laser microvias and sequential lamination

Engineering Impact of the Stack-up

• Signal integrity
• Power integrity
• EMI / EMC
• Mechanical stability
• Reliability
• Manufacturability
• Cost

Do not treat the stack-up AS something the manufacturer fills in later. Layer order and dielectric geometry are part of the electrical and mechanical design.

Plan the stack-up early—before detailed routing begins.

Symmetry • Copper Balance • Reference Planes

A structurally balanced construction and continuous nearby references improve mechanical stability and electromagnetic behaviour.

Balanced Construction

Layer	Thickness (Relative)
L1 Top	0.12
L2 GND	0.18
L3 Sig	0.18
L4 PWR	0.18
L5 PWR	0.18
L6 Sig	0.18
L7 GND	0.18
L8 Bottom	0.12

Strongly Asymmetric Build

Layer	Thickness (Relative)
L1 Top	0.07
L2 GND	0.28
L3 Sig	0.10
L4 PWR	0.28
L5 Sig	0.12
L6 GND	0.08
L7 Sig	0.14
L8 Bottom	0.25

Good Symmetry Practices

• Use similar dielectric thicknesses around the centreline
• Use compatible copper weights on mirrored layer positions
• Avoid heavy copper or large planes on only one side
• Review large copper-free regions and plane voids
• Use fabricator-recommended copper thieving where suitable

Signal Layers & Return Paths

• Place high-speed signals next to a solid reference plane
• Prefer ground as the primary critical reference where practical
• Keep signal-to-reference dielectric relatively thin
• Do not route critical signals across splits or slots
• Add an intentional return transition when changing references
• Do not assume every power plane is a suitable high-frequency reference

Configuration	Description	Field Confinement
Microstrip	Outer signal over an internal reference	Fields extend into air / solder mask
Stripline	Inner signal between reference planes	Strong field containment
Differential pair	Outer or inner coupled conductors	Depends on pair and reference geometry
Broadside differential	Traces on adjacent layers	Requires tight registration control

A symmetrical CAD stack can still laminate poorly when copper density is severely unbalanced.

Controlled Impedance • Materials • Copper • Thickness

Controlled impedance is created by the complete geometry and material system—not trace width alone.

1. Trace Width — +
2. Copper Thickness — +
3. Pair Spacing — +
4. Reference Distance — +
5. Dk — + (symbol shown as εr)
6. Solder Mask — +
7. Copper Roughness — =
8. = — Impedance

Define Before Routing

• Target single-ended and differential impedances
• Controlled layers and reference planes
• Preliminary material family
• Realistic dielectric thicknesses
• Supported copper weights and trace / space
• Permitted manufacturer geometry adjustments
• Tolerance, coupon and report strategy

Key Material Parameters

Parameter	Effect
Dk	Impedance and propagation delay
Df	Dielectric insertion loss
Tg	Glass-transition behaviour
Td	Thermal decomposition
Z-axis CTE	Through-thickness expansion
Moisture absorption	Electrical and reliability effects
Copper profile	High-frequency conductor loss

Copper Terminology; each item shows a cross-section swatch

• Starting / base copper — Foil before processing
• Finished outer copper — Includes plating effects
• Inner copper — Normally etched before lamination
• PTH barrel copper — Separate from planar copper weight

• Cumulative cores + cured prepregs + copper + process variation
• Set tolerance from functional need, not habit
• Tight tolerance can restrict material constructions and increase cost

Obtain a preliminary manufacturer stack-up early, route to it, and require final impedance calculations before production.

Layer Count • Stack-up Strategies • Power Planes

Use the lowest layer count that satisfies routing, SI, PI, manufacturability and production margin without creating a fragile process window.

Layer Count	Conceptual Stack-up Strategy	Typical Use Case
4 layers	Signal / GND / Power-or-Signal / Signal	Simple control and moderate-speed products
6 layers	Signal / GND / Signal / Power / GND / Signal	Additional routing and improved referencing
8 layers	Signal / GND / Signal / Power / GND / Signal / GND-or-Power / Signal	Denser high-speed products
10–12+ layers	Controlled signal layers alternating with solid references	Dense BGA, serial interfaces and high-reliability compute

Conceptual only — Final construction must be engineered with the fabricator

When Extra Layers Are Justified

• Cleaner BGA escape routing
• Dedicated high-speed signal / reference pairs
• Additional solid power or ground planes
• Lower-impedance power distribution
• Improved EMI field containment
• Cleaner layer transitions and return paths

Power & Ground Planning

• Use solid low-impedance ground references
• Place power and ground close where PDN capacitance helps
• Avoid unnecessary plane fragmentation
• Provide adequate copper and vias for high current
• Do not compromise signal references with power splits
• Plan decoupling and stitching using actual layer spacing

Avoid cookbook stack-ups. A layer sequence that works for one board may be poor for another.

Routing density • References • Power architecture • Materials • Vias • Fabricator capability

Vias • HDI • High-Speed • RF • Thermal

Via Technology Matrix

Type	Description	Consideration
Through via	Full board thickness	Aspect ratio and unused stub increase with thickness
Blind via	Outer to internal layers	Depth and process must be defined
Buried via	Internal layers only	Adds lamination complexity
Microvia	Thin build-up dielectric	Reliability depends on geometry and process
Backdrilled via	Unused barrel removed	Controls high-speed stub length
Press-fit PTH	Connector compliant pin	Requires controlled thickness, plating and hole tolerance

HDI Questions to Resolve Early

• Number of sequential lamination cycles
• Stacked or staggered microvias
• Supported laser-drill dielectric thickness
• Maximum qualified microvia stack height
• Via-in-pad fill and copper cap
• Buried-via core drilling sequence
• Reilability verification method

High-Speed Channels

• Tightly reference critical signals
• Consider conductor roughness and dielectric loss
• Minimise layer changes and via stubs
• Keep differential geometry consistent
• Review connector launches and reference transitions
• Model insertion loss, return loss and crosstalk where required

RF / Microwave

• Control Dk, Df, copper foil and dielectric thickness
• Review hybrid-material lamination compatibility
• Agree finish, geometry and test method before layout freeze

Thermal & Mechanical

• Maintain symmetry to reduce bow and twist
• Use planes and thermal vias deliberately
• Consider CTE under thermal cycling
• Protect mechanically critical connector regions

Conventional multilayer approval does not automatically qualify a factory for every HDI construction.

Collaboration • Common Mistakes • Final Review

1. Define electrical, mechanical, material and reliability requirements
2. Select the preferred or candidate manufacturer
3. Manufacturer proposes a supported preliminary construction
4. Review layer functions, references, geometry, copper and impedance
5. Simulate critical high-speed or RF channels where required
6. Confirm vias, thickness and mechanical constraints
7. Approve and freeze before final critical routing
8. Reconfirm at quotation and release
9. Preserve the approved stack-up in the manufacturing record

A Good Stack-up Drawing Shows

• Part number and revision
• Layer number and functional name
• Copper type, weight or finished requirement
• Core / prepreg construction
• Dielectric thicknesses
• Material family / grade
• Overall thickness and tolerance
• Controlled-impedance classes
• Blind, buried, HDI and sequential-lamination structures
• Manufacturer approval revision and date

Common Stack-up Mistakes

Common Mistake	Better Approach
Routing before stack-up	Obtain a manufacturable preliminary build first
Signal next to split plane	Use a continuous nearby reference
Asymmetric build	Balance around the centreline
Ignoring copper density	Review balance and suitable thieving
Treating FR-4 as one material	Define performance or approved family
Arbitrary prepreg thickness	Use supported glass styles and cured builds
Unclear 1 oz copper	State starting versus finished copper
Ignoring via stubs	Plan backdrill or alternate structures
Copying another board	Engineer for the actual product

• Layer count and order justified
• Symmetry and copper balance reviewed
• Critical signals have continuous references
• Material and modelling data are appropriate
• Copper, thickness and impedance are defined
• Trace / space and via aspect ratios are manufacturable
• HDI cycles and special vias are understood
• Thermal, mechanical and warpage risks reviewed
• Manufacturer review completed
• Final approved stack-up is revision controlled

Define objectives • Collaborate early • Route to a real construction • Qualify the final stack-up