Via Types and Manufacturing Considerations

Purpose • Via Families • Selection

Choose the Simplest Structure That Meets the Requirement

Lead Principle: Every additional lamination, drilling, filling or plating step affects cost and process risk.

Item	Detail
1	Plated through via (PTH)
2	Blind via
3	Buried via
4	Microvia
5	Via-in-pad
6	Backdrilled via

Select by Purpose

Item	Detail
Layers to connect	PTH: outer to outer • Blind: outer to inner • Buried: inner to inner • Microvia: thin dielectric • Backdrilled PTH: outer to outer with stub removal
Routing density	Use microvias and blind vias to increase escape density • Via-in-pad to minimise breakout congestion
High speed signals	Minimise stubs: use backdrilling • Avoid unnecessary layer transitions • Follow geometry, antipad and reference rules
Current / heat	Use PTH or via-in-pad for current return and thermal performance • Increase via count or barrel size
Component pad	Via-in-pad for BGAs, LGA, QFN or thermal pads • Ensure controlled fill/planarise/cap for solderable surfaces
Protection / fill	Filled & capped vias provide flat, reliable surfaces • Select conductive or non-conductive fill as required
Inspection & product class	Higher class products need tighter control • Verify capability for build sequence, drill, plate, fill and backdrill

Complexity must be introduced deliberately — not as a routing afterthought.

Choose the simplest via structure that meets the electrical, thermal and mechanical requirement.

Via Types and Manufacturing Considerations

Aspect Ratio • Finished Hole • Annular Ring

1 Aspect Ratio

Aspect ratio = plated depth ÷ hole diameter

Increasing aspect ratio makes desmear, activation and uniform barrel plating harder—raising the risk of thin plating at the centre of the barrel.

Thin plating risk at centre of barrel

Drill-smear and voids can reduce reliability

• Plated Depth
• Hole Diameter

Key Considerations

• Desmear effectiveness decreases with depth.
• Activation coverage is harder to maintain.
• Plating distribution may thin toward the centre of the barrel.

2 Drill Size ≠ Finished Hole

1. Design Intent — Specify finished hole and tolerance.
2. Production Drill — Production drill is generally larger than the required finished opening.
3. Plating / Finish — Plating builds copper to the finished size.
4. Finished Hole — Finished hole meets specified size and tolerance.

For critical press-fit, connector and leaded holes, specify finished hole and tolerance.

Let the fabricator apply drill compensation.

3 Annular Ring & Registration

• Nominal Annular Ring (Artwork Intent)
• Drill Wander (Worst Case)
• Finished Minimum Annular Ring (After Plating)

Drill wander and registration errors reduce annular ring.

Pad diameter, via diameter, artwork registration, plating and layer alignment must be engineered together.

• Soldermask Opening (Top View)
• Pad (Copper)
• Nominal Hole (Artwork)
• Worst Case Hole (After Wander)
• Finished Hole (After Plating)

Hole Geometry Checklist

• Board thickness and layer count defined
• Material type and copper weight confirmed
• Finished hole size and tolerance specified
• Plating requirement (through-hole / via) defined
• Supplier process window understood
• Product class and field reliability considered

Do Not Use One Universal Aspect-Ratio Limit: Evaluate based on board thickness, materials, process capability and product reliability needs.

Nominal Pad-to-Hole Geometry Alone Does Not Prove Finished Annular Ring: Account for drill wander, registration, plating build and layer alignment.

Via Types and Manufacturing Considerations

Blind • Buried • HDI • Microvia Reliability

Blind Via	Buried Via	1+N+1 HDI	Staggered Microvias	Stacked Microvias
Lamination sequence 1→2→3→4	Lamination sequence 1→2→3→4	Lamination sequence 1→2→3→4→5	Lamination sequence 1→2→3→4→5	Lamination sequence 1→2→3→4→5

• Copper
• Prepreg (Dielectric)
• Core (Dielectric)
• Solder Mask
• Filled / Plated Microvia

Why HDI Is Used

Item	Detail
Fine-pitch BGA escape	Escape more balls in a smaller area.
Smaller pads & anti-pads	Enables reduced pad and annular ring sizes.
More routing channels	Increases routing capacity within the same footprint.
Shorter vertical interconnects	Improves signal integrity and reduces stub length.
Via-in-pad capability	Supports dense BGA and fine-pitch interconnects.
Sequential-build architectures	Builds complexity layer-by-layer for maximum density.

Staggered vs Stacked

Staggered (Laterally Offset)

• Interfaces are laterally offset.
• Uses more area.
• Can reduce interface concentration.

Stacked (Vertically Aligned)

• Compact vertical column.
• Filled interfaces and target lands require careful process and reliability control.
• More sensitive to alignment, voids and copper balance.

A microvia is not automatically more reliable.

Cost Follows the Build

Item	Detail
Through vias only	Conventional lamination. • Standard drilling and plating. • Lowest complexity and cost.
One-level microvia	Requires laser drilling. • Fill and plate microvias. • Added process and cost.
Buried + microvia	Uses subassembly cores. • Sequential build-up required. • Higher complexity and cost.
Multiple stacked levels	Repeated build-up interfaces. • Tight process window. • Highest complexity and risk.

Minimise stacked levels. Consider staggered vias, layer reassignment, fan-out changes or a different stack-up first.

Via Types and Manufacturing Considerations

Via-in-Pad • Filling • Thermal Design

Open via-in-Pad

Solder drains into the hole and wicks along the barrel.

Reduced solder volume and higher voiding risk.

Filled, Planarised & Capped via-in-Pad

Maintains solder volume, stand-off and reliability under a BGA.

1. Plate — Via plated per design.
2. Fill — Fill cavity with approved material.
3. Planarise — Remove excess and achieve flat surface.
4. Copper Cap — Plate copper onto planar surface.
5. Finished Land — Solderable land ready for assembly with full solder volume and stand-off.

• Copper
• Prepreg (Dielectric)
• Core (Dielectric)
• Solder Mask
• Fill Material
• Copper Cap

Terminology Matters

Via-in-pad, filled via, capped via and VIPPO are related but not interchangeable.

Tented	Plugged	Filled	Capped / Plated Over
Solder mask covers the opening. • Cavity not filled.	Material intentionally closes or partly fills the hole. • May not be planar.	Cavity filled with a defined material or process. • Surface may require planarisation.	Copper plated over filled, planarised via. • Provides a solderable land at final surface.

Fill Options

• Nonconductive epoxy – Common for planarisation/VIPPO; provides flat surface for solderable land. Copper barrel carries current.
• Conductive fill – Specialised use; material, CTE and reliability must be qualified for the application.
• Copper-filled microvia – Supports stacking and high-density routing; fill and interface integrity are critical.
• Open via – Lowest complexity and cost; unsuitable beneath many solderable pads and for high-reliability assemblies.

Power Vias

Use parallel vias and a complete power delivery strategy.

• Use multiple vias in parallel to share current.
• Design for sufficient barrel copper, finished geometry and plating integrity.
• Consider current sharing, plane connections, and temperature rise through the stack.
• Do not rely on simple “amp-per-via” rules.

Thermal Vias

Evaluate the entire heat path — not just the via.

• Consider via count, barrel copper, planes, fill material, heatsink, and airflow as one thermal system.
• Ensure strong thermal coupling to planes and heatsink.
• Control solder wicking to preserve solder volume and component stand-off.
• Validate with thermal analysis and real-world testing.

An open via beneath a solderable pad can reduce solder volume, increase voiding and upset component stand-off.

Via Types and Manufacturing Considerations

High-Speed • Backdrill • Return Paths

Differential via Transition Through a Multilayer PCB

• Ground return via (close)
• Anti-pad (clearance)
• Signal pad
• Pair symmetry (keep geometry mirrored)
• Signal pad
• Anti-pad (clearance)
• Ground return via (close)
• Return path in reference planes
• Inductive barrel (via inductance)
• Capacitive pad / anti-pad region (via-pad capacitance)
• Inductive barrel (via inductance)

Unused Barrel Stub

Unconnected barrel below last signal layer creates an inductive stub.

• Residual stub

Optional Backdrill

Backdrill removes unused barrel below target depth.

• Backdrill stop depth

Key Design Levers

Item	Detail
Minimise unnecessary via length and stub	Shorter is better for loss, reflections and crosstalk.
Engineer anti-pad geometry	Balance capacitance, clearance and manufacturability.
Place return / stitching vias close	Minimise loop area and return inductance.
Keep differential structures symmetric	Include pads, anti-pads, vias, and reference vias.
Remove nonfunctional pads only when analysis / process allows	Avoid increased mode conversion and impedance steps.
Consider blind / microvia or backdrill	Use when channel analysis shows benefit.
Use 3D em analysis for very high-speed / RF launches	Validate transitions, stubs and return paths with full-wave tools.

Backdrill Drawing Controls

Control	Description / Guidance
Affected vias	Specify which vias are to be backdrilled (IDs or classes).
Drill side	Indicate from Top, Bottom or Both sides.
Start / stop layer or target depth	Define the last functional layer or target depth to stop drilling.
Maximum residual stub	Specify maximum allowed stub length after backdrill.
Diameter / clearance	Backdrill diameter (finished) and required clearance to adjacent copper.
Registration	Tight positional tolerance between original via and backdrill.
Internal nonfunctional-pad breakthrough	Indicate if internal pads may be broken through (yes / no).

Ground Stitching & Shielding

Compact Return Paths

Keep return vias close to the signal vias. Minimise loop area between signal and return.

• Signal
• Ground via
• Return path in plane

Plane Connection & via Fences

Use via fences to contain fields, prevent mode conversion and reduce radiation.

• Ground via fence
• Signal via (diff pair)

Spacing Is Electromagnetic, Not Visual

Set spacing and density based on impedance control, field containment and return current behaviour — not on visual patterns or marketing rules.

Backdrill must be driven by channel analysis and stub length — not data-rate marketing numbers alone.

Differential pair symmetry includes vias, anti-pads, planes and reference vias.

Control, Qualify and Release

Control • Qualification • Release

1. Purpose
2. Via Architecture
3. Fabricator Capability
4. Controlled Drawing
5. Representative Coupon
6. Thermal / Reflow Test
7. Microsection + Resistance Evidence
8. Release

Fabrication Drawing – Define

Item	Define
PTH	finished hole, pad, plating / performance requirement.
Blind / buried	start layer, stop layer, hole and build sequence.
Microvia	layer pair, diameter / pad, fill, stacked or staggered.
Via-in-pad	fill, planarise and cap / plated-over condition.
Backdrill	side, affected vias, depth / stop, residual stub and diameter.
Press-fit	connector-specific finished hole / tolerance and plating.
Protected via	tented, plugged, filled or capped finished condition.

Reliability Evidence

Item	Detail
Microsection – Barrel plating and interfaces	Uniform copper thickness, complete coverage and sound copper-to-copper interfaces.
Registration	Layer-to-layer alignment within process capability.
Microvia target-pad interface	Adequate land, centred via, no breakout or pad lift.
Fill / voids (AS applicable)	Voids within limits or fully filled as specified.
Backdrill residual stub	Measured stub length within specification.
Representative via-chain coupons	Test worst-case structures and longest signal paths.
Lot / panel traceability	Coupon ID linked to panel/lot, process parameters and inspection records.
Thermal / reflow resistance monitoring	Controlled thermal profile and monitoring; pass/fail criteria met.

• Coupon ID 12345-ABC-01
• Temp
• Preheat
• Soak
• Reflow
• Cool
• Time

Common Mistakes

• Smallest advertised via.
• Ignored aspect ratio.
• Open pad via.
• Many stacked levels.
• No return vias.
• Ignored stub.
• Vague “filled via”.
• Manual drill compensation.
• Tiny pads without registration margin.
• No representative coupons.
• Too many special processes without early DFM.

A visually acceptable microsection may not be sufficient evidence for a complex high-reliability microvia structure.

Final Release Check

Item	Detail
Simplest architecture used	Use the least complex structure that meets the performance requirement.
Qualified supplier window	Design within the supplier’s qualified process window.
HDI build reviewed	Layer build, sequence and materials reviewed and approved.
Stacked levels minimised	Minimise stacked microvias and total via levels to reduce risk.
Current/thermal/high-speed needs assessed	Verify current, thermal and signal integrity requirements are achieved.
Terminology precise	Use accurate, consistent terms and requirements.
Drawings and coupons controlled	Controlled revision, coupon IDs and change management.
DFM and capability approval complete	DFM review and supplier capability approval on file.

Choose the simplest manufacturable architecture and verify critical interconnects with traceable evidence.